A first-in first-out (FIFO) buffer uses counters, adders and combinatorial logic to generate a half empty and/or a half full flag. FIFOs can also generate programmable empty and programmable full flags having a user programmed offset ahead of the respective boundary flags. The programmable empty and programmable full flags are generated by computing the difference between the write and read counters and comparing this magnitude with the user programmed offset. The read and write counters arc reset to zero upon master reset.
A copending application, Ser. No. 08/572,623, provides a state machine design which can be used to realize extremely short delays in generating half-full and half-empty flags and is hereby incorporated by reference in its entirety. The copending application generates a set of next state variables from a combination of three previous state variables and three additional inputs representing a logical OR of a read half-full and write half-full flag, an external write clock input and an external read clock input.
The inputs to the state machine (used to generate the status flags) are derived using an internal half-full decode logic having variations of the read and write clocks as inputs. The output of the decoder that is fed to the state machine inputs may have glitches. Glitches are generally defined as a transient state where a signal, in this case the output of the decoder, fluctuates between digital states (i.e., a digital one and a digital zero). The width (i.e., the length of time in the transient state) of the glitches is a function of the current read and write counter values. The state machine can be designed to handle these glitches internally at the expense of having an increased complexity.
Previous approaches to minimize the width of a glitch produced by a decoder circuit generally include sizing down the NMOS devices in the NOR gates as well as the PMOS devices in the NAND gates and adding a delay to allow the circuit to settle into a glitch-free steady state value. Essentially, the NOR and NAND gates delay producing an output until the glitch has passed. The disadvantage of such an approach is that the delay which is necessary to improve the function (by reducing glitches) slows down the circuit.
Other methods to reduce glitches are to employ edge preferential delays to use, to use non-overlapping clock generators or to add magnitude comparators. However, each of these methods slows down the overall performance of the underlying flag generation circuit.